1. Field of the Invention
The present invention is related to monolithic memory arrays of the type implemented on semiconductor chips, and in particular to a fault tolerant memory array having block redundancy.
2. Description of the Prior Art
Large scale integration (LSI) techniques have made possible the construction of memory devices having large arrays of binary storage elements on a single chip of silicon. The immediate advantages for such arrangements are the high cell density and low power requirements. In the production of monolithic chips, it is not unusual for the yield of good chips from a silicon wafer to be low, especially during early production runs. For each perfect chip produced, there a number of chips that are almost perfect, having one or more localized defects which render unusable a single cell or a few closely associated cells or clusters of cells.
It will be appreciated that the presence of only one defective cell in an otherwise perfect memory array can render useless the entire memory array.
As cell density increases, the likelihood of processing defects increases. Therefore there is a continuing interest in techniques for improving the yield of perfect arrays, and for repairing or otherwise rendering usable those memory arrays having processing defects.
Several prior art approaches have been implemented for improving yield. For example, error correction codes have been used to correct words read from a memory in which certain bits of a word are stored in defective cells. According to another approach, a discretionary wiring technique is used during processing to bypass defective cells. Additionally, defect-tolerant memory systems have been disclosed in which an entire redundant row or column of cells is substituted for a selected row or column containing one or more defective cells. In such an arrangement, a redundant row of perfect cells is substituted for a row having one or more defective cells by storing the word address of the defective row in a content addressable memory along with the address of the redundant row.
In yet another fault tolerant arrangement, a cell addressable array utilizes a redundant row of cells together with a defective word address register and a comparator circuit for disabling a defective row of cells and replacing it with a redundant row of cells. The word address is stored either by selectively open-circuiting conductive paths in a read only memory, or by selectively grounding bits of the read only memory.
In each of the foregoing fault tolerant arrangements, whether the memory be of the word addressable or cell addressable type, a requirement in each is that at least one redundant line of cells be provided for each row or column in which one or more bad cells exist. Further, faulty bit locations of a memory array can be tolerated only to the extent that rows or columns in which such faulty locations exist do not exceed the total number of redundant rows provided.
Additionally, cell and word addressable arrays typically include decoders, input/output logic, and other overhead circuitry, in which processing defects may occur, and which cannot be cured by word addressable or cell addressable techniques.